Microprocessor performance has seen incredible increases over the short history of computers. With this increase in processor performance, seen in the increased number of processor cycles per second, has come the heed for a comparable increase in access speed to data and instructions. Otherwise, it provides little benefit to have a very fast processor if it is spending most of its time waiting for retrieval of data and instructions from storage devices such as disk and tape drives. In order to achieve fast transfer rates between a peripheral and a processor it was common to use a parallel communications interface in order to maximize the data transfer rate. In such a parallel communications interface it was typical to transmit a full word (usually 32 bits) at the same time using at least one wire per bit. However, more recently, serial communications has so significantly increased in speed that up to 1.5 gigabits per second of data may be transferred over a Serial ATA communications link.
FIG. 1 is an example of such a Serial ATA communications link 30 connecting a peripheral device 40 to a processor 10 located on a baseboard 20. Utilizing such a communications link 30 the number of wires required to connect a peripheral device, such as a disk drive, CD-ROM, DVD or other peripheral device is substantially reduced. Data may be transferred over such a Serial ATA communications link 30 in the form of bits, bytes, or more typically packets. Packets of data may contain as much as 8,192 bytes of information, but any size packet is possible.
However, in such a Serial ATA communications link, buffer space is required both in the baseboard 20 and the peripheral device 40 in order to store one or more packets of information being transferred. This buffer space is required due to the CRC (cyclical redundancy checking) error checking technique being used in the Serial ATA communications protocol. CRC is an error checking technique used to determine the integrity of received data. However, the CRC error check is complete only after the entire packet is received. Therefore, it is necessary to store the received data temporarily in a buffer while performing the CRC error checking, and then determine whether the packet was correctly received. In the case where an error is detected, retransmission is requested for the entire packet by the receiving device. Therefore, valuable space is required on the baseboard 20 and in the peripheral device 40 to store these packets of data until they are checked using the CRC error checking technique. Further, in the case where there is an error, valuable time is wasted in order to transmit the retransmit request and receive the entire packet at least twice in order correct the error.
Therefore, what is needed is a device, method, and computer program that allows the received Opcode of an incoming packet to be decoded and verified as correct immediately upon receipt. This device, method, and computer program minimizes the need for buffer space in the receiving unit by allowing the Opcode to be decoded and acted upon before the CRC check for the complete packet is done.